User guide

20-67
Using OpenVera Assertions
• The -ova_exp_param option is not enabled.
• Any modules to which units using Verilog parameters are bound
occur only once in the design
• Multiple instances of any modules to which units using Verilog
parameters are bound use the same value for each parameter
across all instances.
In other words, if any one module is instanced multiple times with
different parameter values for two or more of the instances, then the
parameter expansion that occurs at the time the inlined OVA is
extracted will render the generated.ova file unusable for other
purposes.
Post-processing Flow
A small change to the post-processing flow is necessary in order for
this enhancement to have an effect on the OVA code compiled for
post-processing. Recall that, normally, inlined OVA is not supported
in the post-processing flow. However, it is still possible to invoke the
inline pre-processing step as part of this flow.
Use Model
The existing post-processing flow consists of three basic steps:
1. Compilation of the design (Verilog) files using -ova_PP,
2. Compilation of the OVA source files using -ova_RPP
3. Replay of the saved simulation vectors with OVAPP