User guide

20-66
Using OpenVera Assertions
Recommended Methodology
To make use of Verilog parameters in temporal context, the binds
that use such parameters must follow the inlined OVA flow. For OVA
binds which are already inlined into the RTL, no additional work is
required. It is not necessary, however, that the bind statements be
inserted directly into the RTL source. Rather, a separate file (such as
dummy.v) could be created to hold all the binds in the design that
come from separate (non-inlined) OVA files. Giving this file a ".v"
extension and passing it to the compiler with -ova_inline and
-ova_exp_param enabled is enough to get the inline preprocessor
to substitute the parameter value for the parameter name before
passing the converted OVA code to the OVA compiler.
To avoid future problems, we also recommend moving the binds that
are not already inlined into one or more of these dummy Verilog files.
That way, if the contents of the OVA unit change at some point in the
future (for example, a new parameter used in temporal context is
added when there was previously no such parameter), the bind will
continue to work as expected. Also, while other OVA code (such as
units or templates) can be added to these dummy Verilog files, we
do not recommend this, as there is some chance of confusing the
inline processor (which, at this point, does not use a very
sophisticated parser).
Caveats
The inline pre-processor writes the extracted inlined OVA into a file
called generated.ova under the ova.vdb directory hierarchy. In the
past, this file could be copied into a user-level file and used in
subsequent simulation runs as a block of extracted OVA. This can
still be done, to a certain extent. However, one of the following must
be true: