User guide

20-65
Using OpenVera Assertions
For example, the following binds would not be legal if count and delay
were used by the bound unit in temporal context:
/*
ova bind module foo : unitA u1 #( count ) ( ... );
ova bind module bar : unitB u2 #( delay ) ( ... );
*/
// ova_begin
ova bind module foo : unitA u1 #( count ) ( ... );
ova bind module bar : unitB u2 #( delay ) ( ... );
// ova_end
The parameter names are resolved in the context of the module to
which the unit is bound. If the unit parameter is used in temporal
context, the Verilog parameter bound to that unit must not use a
cross-module reference (cross-module references are allowable if
the parameter is only used in static context). Both module and
instance binding is supported by this enhancement. But only binds
directly found in pragmas in the Verilog file will be recognized. Bind
statements inside files which are included in one or more Verilog files
via ‘include will not be processed.
Table 20-3 Verilog Parameter Use Model Summary
Parameter context: Static (bus width) Temporal (delay, repeat, ...)
Type of bind Module or instance Module or instance
Location of bind Inline or separate file Inline flow only
XMR parameters
allowed
Yes No
Pragma format Single or multiple line Single line only (// ova bind)
Can put bind in
include file
Yes No