User guide

20-64
Using OpenVera Assertions
The enhancement described in this document will cause the Verilog
parameters to be expanded at the time the inlined OVA is processed
by the OVA extractor, since the OVA binds and the design hierarchy
are both available at that time. This implies that Verilog parameters
can only be used in temporal context if the parameter was first
expanded during the inlining phase. For that reason, only inline OVA
binds will be able to pass Verilog parameter values to a unit if the
parameter is to be used in a temporal context.
Enabling Verilog Parameter Expansion
To enable the substitution of Verilog parameters during inlining, the
-ova_exp_param option must be used on the command line at
compile time. In addition, the -ova_inline option must be enabled
in order to enable the OVA inline processing.
Limitations on the Input
Only those binds found in single-line pragmas will be scanned for
Verilog parameters (this is an internal limitation of the OVA inline
parser). In order to use a Verilog parameter in temporal context via
an OVA bind statement, the bind statements must be of the form:
// ova bind module foo : unitA u1 #( count ) ( ... );
// ova bind module bar : unitB u2 #( delay ) ( ... );
// ova bind ...etc...
Multiple-line inline pragmas (mostly used for full-language inlining)
follow a different flow when they are processed and will not work if
Verilog parameters are used in temporal constructs (but they will
continue to work correctly for binds containing constants or Verilog
parameters used only in static context).