User guide

20-63
Using OpenVera Assertions
Using Verilog Parameters in OVA Bind Statements
This section describes the enhancement to VCS that allows Verilog
parameters to be used in temporal context in OVA bind statements.
This enhancement is under an optional switch. At this time, use of
Verilog parameters is limited to inline bind statements, but simple
workarounds exist to allow binding of non-inline OVA while still
allowing full use of Verilog parameters.
For purposes of this document, a value is used in temporal context
if it is used as a delay (or delay range), a sequence length (or length
range), or as a repeat count in an OVA event or assert statement. A
value is used in static context if it is used to compute the bit width or
bounds of a vector in an OVA unit statement.
Use Model
The current OVA use model allows the use of Verilog parameters
only in static context. That is, the vector widths of an OVA unit may
be defined using Verilog parameters. This continues to be the case
even after this enhancement.
However, the OVA compiler does not have access to the Verilog
parameters at the time the OVA state machine is compiled. The
values of the parameters must be extracted and passed to the OVA
compiler in order to use these values in temporal context.