User guide

20-60
Using OpenVera Assertions
If the off argument is specified, full case checking is disabled unless
overridden by another command or a pragma associated with a case
statement.
When the pragma is not specified, the default is off.
The following rules govern parallel and full case commands:
• The commands must precede any module instance and any case
statement in the module.
• If such a command is not provided, the default from the parent
module is taken. (It can be by default off.) Also, you must make
sure that every instance of the child module receives the same
specifications. To avoid this limitation, widely used modules
should include case-checking specifications.
• If a case statement appears in a function or a task, the module
that contains the function or task declaration determines the
default case checks (unless overridden by a local case pragma
on the case statement).
Context-Dependent Assertion Pragmas
OVA includes three local assertions that depend on the context in
which they are placed in the Verilog code:
// ova parallel_case;
// ova full_case;
// ova no_case;
The pragma must be placed immediately following a case
(expression) statement. If placed anywhere else, an error will be
reported. They apply only to the associated case statement. The
defaults continue to apply elsewhere.