User guide

20-58
Using OpenVera Assertions
Inlining Context-Dependent Full Custom OVA
You can directly inline any custom OVA code, except for the unit
definition, within a Verilog module. In this case, the unit and binding
definitions are implicit.
The following example demonstrates this method:
module test();
reg clk;
wire a,b;
// other verilog code
// ova_begin
// clock posedge clk {
// event e1 : a #1 b;
// }
// assert a1 : forbid(e1);
// ova_end
/* ova
clock posedge clk {
event e2 : ended(e1) #2 b;
}
assert a2 : forbid(e2);
*/
// more verilog code
endmodule // module test
Uses modified C++ style pragma to
specify custom OVA code that defines
event e1 and assertion a1.
Uses C++ style pragma to
specify custom OVA code
that defines event e2 and
assertion a2.