User guide

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Getting Started
Making a Verilog Model Protected and Portable
After you have successfully verified your design using VCS, you can
use the Verilog Model Compiler (VMC) to make the design portable
and protected. VMC enables you to secure your design and distribute
it to your partners and internal or external customers without a Non
Disclosure Agreement (NDA).
VMC is a model development tool used to generate portable models,
starting with Verilog source and producing compiled SWIFT models.
SWIFT is a language- and simulator-independent interface that
allows your model to run with any SWIFT-compatible simulators;
more than thirty simulators are now available.
VMC models contain no Verilog source code, so they protect the
intellectual property of the underlying design. This enables model
developers to distribute their models without revealing the contents,
because the models are secure. More importantly, the models are
functionally exact because they are derived from the original Verilog
description of the model.