User guide

20-56
Using OpenVera Assertions
Template Instantiation Using the Template-Based
Checker Library
You can instantiate any template-based checker from the Checker
Library in your Verilog code. The context of the checker is
automatically inferred based on the location of the call from within
Verilog.
Note the following construct usages and limitations in template
Instantiation:
• Clocks must use edge expressions (unit-based checkers use
Verilog style ports)
• You can specify the default clock in conjunction with the
check_bool and forbid_bool checkers, however, it does not
work with other templates or units. The following example shows
a supported default clock:
//ova clock posedge clk;
Note that each sequence or boolean expression is associated
with a clock. The clock determines the sampling times for variable
values.
• Both for loops and nested for loops are supported, as shown
below:
for (name=expr;name op1 expr;
name=name op2 expr)
{
for loop body
}