User guide

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Using OpenVera Assertions
Inlined OVA is enabled in VCS by the -ova_inline command line
switch.
Specifying Pragmas in Verilog
Inlined OVA is specified in Verilog code using pragmas. Several
different forms are accepted, including C and C++ style comments,
and modified C++ multi-line comments.
The general C++ style form is as follows:
/* ova first_part_of_pragma
...
last_part_of_pragma
*/
You can also use the following modified C++ approach:
//ova_begin
// pragma_statement
//...
//ova_end
For a single-line pragma, you can use the following C form:
// ova pragma_statement;
Assertions can be placed anywhere in a Verilog module and they use
predefined units, including those in the Checker Library.