User guide

20-48
Using OpenVera Assertions
Using OVA with Third Party Simulators
Synopsys has developed OVAsim, a PLI application that enables you
to run non-Synopsys simulators using OVA (OVA). With OVAsim, you
can create a powerful system of assertion-based checkers. Because
the checkers are compiled independently of a specific simulator, they
can be used with any major simulator, packaged with IP designs, and
shipped to any customer.
OVAsim works by compiling the OVA code into a shared object and
creating a wrapper file that forms the link between the checkers and
the design. This wrapper file provides ports to the signals of interest
in the design and contains all necessary PLI calls. Also, because the
OVA code specifically refers to the ports of the wrapper file, it is largely
insulated from design changes. The wrapper file and shared object
generated by OVAsim are compiled and run as a part of the design
by the simulator.
For more information on OVAsim, contact
[e-mail].
Inlining OVA in Verilog
Inlined OVA enables you to write any valid OVA code within a Verilog
file using pragmas. In most usage cases, the context is inferred
automatically and the OVA code will be bound to the current module.
You can use this process with or without regular OVA files. The results
for both inlined and regular (OVA) assertions are reported together.