User guide

1-19

Getting Started

% simv -l log +notimingcheck

Basic Runtime Options

This section outlines some of the basic runtime options you can use

to control how VCS compiles your Verilog source files. Detailed

descriptions and usage instructions for all runtime options are

available in Chapter 4, "Simulating Your Design" and Appendix C,

"Simulation Options".

Here:

Specifies monitoring for the specified type or types of coverage.

The arguments specify the types of coverage:

line

Monitor for line or statement coverage.

cond

Monitor for condition coverage.

fsm

Monitor for FSM coverage.

tgl

Monitor for toggle coverage.

path

Monitor for path coverage.

branch

Monitor for branch coverage

-l filename

All output of simulation is written to the file you specify as

filename, as well as to the standard output.