User guide

20-26
Using OpenVera Assertions
Building and Running a Post-Processor
The procedure to build and run a post-processor is as follows:
1. Include either of the following in your Verilog code:
- The $vcdpluson system task to tell VCS to write a VPD file
during simulation.
Note: Use the -PP compile-time option to write the VPD files
as described in the following step.
- The $dumpvars system task to tell VCS to write a VCD file
during simulation.
If VCS writes a VCD file, the post-processor will call the vcd2vpd
utility to translate it into a VPD file.
Note:
Do not use the -ova_PP compile-time option to generate design
dumps for OVAPP. Such dumps will not contain all the correct
hierarchies needed.
2. Compile your design with the -ova_PP compile-time option, for
example:
vcs -f filename -ova_PP [-PP] [-o simv_name]
[-ova_dir directory_path]
In this example compilation command line:
-f filename
Specifies a file containing the source files, and perhaps
compile-time options. This compile-time option is not
specifically related to OVA post-processing.