User guide

20-25
Using OpenVera Assertions
• Post-process a compiled design several times with different
temporal assertions files each time. You can observe the effects
of different assertion scenarios and collect several distinct sets of
functional coverage data.
• Develop assertions incrementally over a series of post-processing
runs, improving and augmenting the assertions in the process.
OVAPP Flow
The following steps show a typical flow for post-processing a compiled
VCS design with temporal assertions.
1. To use the post-processor CLI as the debugging tool, include the
$vcdpluson or the $dumpvars system task in your Verilog
code.
2. Compile your design in VCS with the -ova_PP compile-time
option.
Note:
Use the $vcdpluson or the $dumpvars system task in your
Verilog code to create dump files and enable CLI functionality.
Do not use the -ova_debug compile-time option.
3. Simulate the design to create a VPD or VCD file.
4. Build the post-processor.
5. Run the post-processor using DVE or the post-processor CLI.