User guide

1-18
Getting Started
On Solaris, HP, and Linux machines, VCS can generate object files
from your Verilog source files and does so by default. This is
sometimes called native code generation. On these machines, if you
enter the -gen_asm or -gen_c compile-time options, VCS generates
corresponding intermediate assembly or C files and then assembles
or compiles these intermediate files into object files.
On DEC Alpha, and IBM RS/6000 AIX, VCS always generates
intermediate C files. The -gen_c compile-time option is a default
option on these platforms.
Running a Simulation
To run a simulation, you simply specify the name of the executable
file (produced from the compilation process) at the command line.
The command line syntax for running a simulation is as follows:
executable_file options
Here:
executable_file
The executable file that is created by the vcs command, which
compiles your source code and links your design with VCS to form
the executable.
options
Runtime options that specify how to simulate your design. Some
of the basic runtime options are described in “Basic Runtime
Options” on page 1-19".
For example, the following command line can be used at runtime: