User guide

20-6
Using OpenVera Assertions
Figure 20-1 Assertion Attempts for cnt.ova
Important:
Synopsys recommends always specifying a clock signal for an
assertion. An assertion without a clock is called a simtime assertion.
VCS checks simtime assertions with a default clock that is the
equivalent to the smallest time precision in the design and this
significantly impedes simulation performance. When VCS compiles
a simtime assertion, it displays a warning message.
A OpenVera testbench can monitor and control the testing. Using
built-in object classes, you can stop and start attempts to match the
selected assertion; monitor attempts, failures, and successes; and
synchronize the testbench with the testing process.
How Event Coverage Is Tested Using the cover Directive
The cover directive records only successful matches. You can
specify the cover directive specific to your design or use it with
assertions statements.
With the default compile-time options, only one counter is generated
for each cover directive. This counter is incremented each time the
event expression matches. At the end of a default simulation, the
number of total matches is reported in the example:
unit_instance_name cover_name, int_val total match
1234567891011121314posedge m_clk
outp
c_normal_s
06 04 0408 06 09 03 0d 0e 04 06 09 06