User guide

20-5
Using OpenVera Assertions
Example 20-1 Temporal Assertion File, cnt.ova
/* Define a unit with expressions and assertions (or select
one from the Checker Library).
*/
unit step4
#(parameter integer s0 = 0) // Define parameters
(logic clk, logic [7:0] result); // Define ports
// Define a clock to synchronize attempts:
clock posedge (clk)
{
// Define expressions:
event t_0 : (result == s0);
event t_1 : (result == 6);
event t_2 : (result == 9);
event t_3 : (result == 3);
event t_normal_s: t_0 #1 t_1 #1 t_2 #1 t_3;
}
// Define an assertion:
assert c_normal_s : check(t_normal_s, "Missed a step.");
endunit
/* Bind the unit to one or more instances in the design.
*/
// bind module cnt : // All instances of cnt or
bind instances cnt_top.dut : // one instance.
step4 start_4 // Name the unit instance.
#(4) // Specify parameters.
(m_clk, outp); // Specify ports.
When the temporal assertion file is compiled and run, the assertions
are continuously tested for the duration of the simulation. New
attempts to match each assertion to the simulation’s values are
started with every cycle of the assertion’s associated clock. Each
attempt continues until it either fails to match or succeeds in matching
the complete expression (see Figure 20-1). The up arrow at clock tick
7 indicates a match that started at tick 4. The down arrows are failures.
The failure or success of each attempt is logged to a file that you can
review later.