User guide

20-2
Using OpenVera Assertions
• Using Verilog Parameters in OVA Bind Statements
• OVA System Tasks and Functions
For a detailed decsription of OpenVera Assertions, see the OpenVera
Assertions Language Reference Manual.
Introducing OVA
OVA is a clear, easy way to describe sequences of events and
facilities to test for their occurrence. With clear definitions and less
code, testbench design is faster and easier, and you can be confident
that you are testing the right sequences in the right way.
As a declarative method, OVA is much more concise and easier to
read than the procedural descriptions provided by hardware
description languages such as Verilog. With OVA:
• Descriptions can range from the most simple to the most complex
logical and conditional combinations.
• Sequences can specify precise timing or a range of times.
• Descriptions can be associated with specified modules and
module instances.
• Descriptions can be grouped as a library for repeated use. OVA
includes a Checker Library of commonly used descriptions.
Built-in Test Facilities and Functions
OVA has built-in test facilities to minimize the amount of code that
you need to write. In addition, OVA works seamlessly with other
Synopsys tools to form a complete verification environment.