User guide

19-40
Using the VCS / SystemC Cosimulation Interface
The Verilog adapter is a group of task definitions and other
statements that must be included in a program with an
`include "if_name_sc_calls_sv.sv" statement. Calls
initiated by the SystemC side are routed through the XMR path
to some class object of the SV testbench.
• combination -tli_gen_class, no hdl-path:
This combination is not supported and displays an error message.
It is important to note that Verilog tasks, in contrast to Verilog
functions, must always be called from within a SystemC thread
context. This is because tasks can consume time, and in order to
synchronize the simulator kernels, wait() is used in the SystemC
adapter module. The SystemC kernel throws an error when wait()
is called from a non-thread context.
Supported Data Types of Formal Arguments
The TLI infrastructure uses the SystemVerilog DPI mechanism to call
the functions and transport data, so the basic type mapping rules are
inherited from this interface. Refer to the SystemVerilog standard for
a detailed description on DPI. In summary, the following mapping
rules apply for simple data types:
SystemVerilog SystemC
input byte char
inout | output byte char*
input shortint short int
inout | output shortint short int*
input int int
inout | output int int*
input longint long long