User guide

19-39
Using the VCS / SystemC Cosimulation Interface
format of debug information that the adapter prints when an interface
method is called. If the LSB of this argument is set, the TLI adapter
prints messages to stdout. If the next bit (LSB+1) is set, this
information is written to an sc_signal string that you can display
in DVE.
For SystemC calling SystemVerilog, the SystemC part of the TLI
adapter is an sc_module that you can instantiate within the module
where you want to call the Verilog tasks or functions. You can execute
the cross-boundary task or function calls by calling the corresponding
member function of the SystemC TLI adapter instance.
The SystemVerilog portion of the TLI adapter depends on whether
the hdl_path field is used and options -tli_gen or
-tli_gen_class is used:
• combination -tli_gen, no hdl_path:
The Verilog adapter has a port over the interface type, as defined
in the interface description file. You can instantiate the adapter
module in the Verilog design like any other Verilog module, and
the port should be bound to the SystemVerilog interface that
implements the tasks or functions to be called.
• combination -tli_gen, with hdl_path path:
The Verilog adapter is a Verilog module with no ports. All calls
initiated by SystemC are routed through the XMR path to some
other Verilog module or interface.
• combination -tli_gen_class, with hdl_path path: