User guide

19-30
Using the VCS / SystemC Cosimulation Interface
vcs -sysc -R -o simv top.v
If you instantiate Verilog code in SystemC:
syscsim -R -o simv dev.v
Debugging Both the Verilog and SystemC Portions of a
Design
To debug both the SystemC and Verilog portions of your design:
1. Run syscan with the -cflags "-g" option to build the SystemC
source code for debugging.
2. Include the -debug_all compile-time options on the vcs or
syscsim command line to compile the Verilog part of the design
for post-processing debug tools and for Verilog source code
debugging.
To compile and interactively debug a Verilog design containing
SystemC modules, enter command lines like the following:
vcs -sysc -debug_all top.v
To compile and interactively debug a SystemC design containing
Verilog modules, enter command lines like the following:
syscsim -I -line
3. Start the C++ debugger on the simv executable file. As DVE is
already running the simv executable, you must attach your
debugger to the simv process.
4. To find the simv executable process ID, execute the following
command: