User guide

19-29
Using the VCS / SystemC Cosimulation Interface
Verilog * bit_vector uchar
Verilog * bit_vector short
Verilog * bit_vector ushort
Verilog * bit_vector uint
Verilog * bit_vector long
Verilog * bit_vector ulong
Debugging the SystemC Portion of a Design
To debug just the SystemC code in the mixed simulation, do the
following:
1. Run syscan with the -cflags "-g" option to build the SystemC
source code for debugging.
2. Start the C++ debugger on the simv executable file as follows:
- If you are using the Sun Forte compiler:
dbx ./simv
- If you are using the Gnu compiler on Solaris or Linux:
Run both syscan and VCS with the -cpp path option.
gdb ./simv
You can now set and stop at breakpoints in your SystemC code.
Debugging the Verilog Code
To debug the Verilog code, create the simv executable with the -RI
option to start VirSim for interactive debugging, for example if you
instantiate SystemC code in Verilog code: