User guide

19-27
Using the VCS / SystemC Cosimulation Interface
The following example shows a port mapping file.
Example 19-1 Port Mapping File
# Port name Bits Verilog type SystemC type
in1 8 signed sc_int
in2 8 bit_vector sc_lv
clock 1 bit sc_clock
out1 8 bit_vector sc_uint
out2 8 bit_vector sc_uint
SystemC types are restricted to the sc_clock, sc_bit, sc_bv, sc_logic,
sc_lv, sc_int, sc_uint, sc_bigint, and sc_biguint data types.
Native C/C++ types are restricted to the bool, char, uchar, short,
ushort, int, uint, long, and ulong data types.
Using a Data Type Mapping File
When running a VCS / SystemC simulation, the interface propagates
data through the module ports from one language domain to another.
This can require the interface to translate data from one data type
representation to another. This translation is called mapping and is
controlled by data type mapping files.
The data type mapping mechanism is similar to that used for port
mapping, but is more economical and requires less effort to create
and maintain. Because the data type mapping is independent of the
ports, you can create one or more default mappings for a particular
type that will be used for all ports, rather than having to create a port
map for every port of each new HDL wrapper model.
Data type mapping files map types, so that ALL ports of that type on
ALL instances will now be assigned the specified mapping.