User guide

19-26
Using the VCS / SystemC Cosimulation Interface
Using a Port Mapping File
You can provide an optional port mapping file for the syscan
command with the -port option, and for vlogan by using
-sc_portmap. If you specify a port mapping file, any module port
that is not listed in the port mapping file is assigned the default type
mapping.
A SystemC port has a corresponding Verilog port in the wrapper for
instantiation. The syscan utility uses the entry for the port in the port
mapping file.
A port mapping file is an ASCII text file. Each line defines a port in
the SystemC module, using the format in Example x and y. A line
beginning with a pound sign (#) is a comment.
A port definition line begins with a port name, which must be the same
name as that of a port in the HDL module or entity. Specify the number
of bits, the HDL port type, and the SystemC port type on the same
line, separated by white space. You can specify the port definition
lines in any order. You must, however, provide the port definition
parameters in this order: port name, bits, HDL type, and SystemC
type.
The valid Verilog port types, which are case-insensitive, are as
follows:
• bit — specifies a scalar (single bit) Verilog port.
• bit_vector — specifies a vector (multi-bit) unsigned Verilog
port (bitvector is a valid alternative).
• signed — specifies a Verilog port that is also a reg or a net
declared with the signed keyword and propagates a signed value.