User guide

19-21
Using the VCS / SystemC Cosimulation Interface
In this example, dev.v might contain Verilog code utilized by the
adder.v module above.
When you compile with this option, VCS looks in the ./csrc directory
for the subdirectories containing the interface and wrapper files
needed to connect the Verilog and SystemC parts of the design.
Elaborating the Design
When SystemC is at the top of the design hierarchy and you
instantiate Verilog code in the SystemC code, the elaboration of the
simulation is done in the following two steps:
1. The first step is to create a temporary simulation executable that
contains all SystemC parts but does not yet contain any Verilog
parts. VCS then starts this temporary executable to find out which
Verilog instances are really needed. All SystemC constructors
and end_of_elaboration() methods are executed; however,
simulation does not start.
2. VCS creates the final version of the simv file containing SystemC
as well as all HDL parts. The design is now fully elaborated and
ready to simulate.
As a side effect of executing the temporary executable during step
1, you will see that the following message is printed:
INFO: Exiting prematurely since $SYSTEMC_ELAB_ONLY is set
In case your simulation contains statements that should NOT be
executed during step 1, guard these statements with a check for
environment variable SYSTEMC_ELAB_ONLY or the following
function: