User guide

19-20
Using the VCS / SystemC Cosimulation Interface
The module name is adder. You instantiate it in your SystemC code
in main.cpp as follows:
#include <systemc.h>
#include "adder.h"
int sc_main(int argc, char *argv[]){
sc_clock clock ("CLK", 20, .5, 0.0);
sc_signal<sc_lv<32> > value1;
sc_signal<sc_lv<32> > value2;
sc_signal<sc_lv<32> > result;
// Verilog adder module
adder adder1("adder1");
adder1.value1(value1);
adder1.value2(value2);
adder1.result(result);
sc_start(clock, -1);
}
One of the generated files is modulename.h, which you should
include in your top.cpp file.
Compiling a SystemC Design Containing Verilog
Modules
When you compile your design, you must include the hierarchy path
to the SystemC wrapper instances on your design compilation
command line. For example:
syscsim dev.v other_C++_source_files compile-time_options
adder=adder1