User guide

19-16
Using the VCS / SystemC Cosimulation Interface
Figure 19-2 VCS DKI Communication of SystemC Design Containing
Verilog Modules
Input Files Required
To run cosimulation with a SystemC design containing Verilog
modules, you need to provide the following files:
• Verilog source code (.v extensions)
- You can directly write the entity-under-test Verilog code or
generate it with other tools. The Verilog description represented
by the entity-under-test can be Verilog code of any complexity
(including hierarchy) and can use any language feature VCS
supports.
- Any other Verilog source files necessary for the design.
DKI
clk
reset
in
out
rdy_read
HDL simulatorSystemC environment
clk
reset
in
out
rdy_read
SystemC interface to the
HDL simulator
HDL interface to the SystemC environment
Automatically generated by the tool
Managed by the tool
Block 2
Block 1
Block 2
Block 3
Block 1
HDL source code
entity-under-test
SystemC source code