User guide

1-13
Getting Started
Compiling the Simulation Executable
After setting up your environment and preparing your source files,
you are ready to compile a simulation executable. To create this
executable, named simv by default, use the following VCS command
line:
vcs source_files [source_or_object_files] options
where:
source_files
The Verilog, OpenVera assertions, or OpenVera testbench source
files for your design. The file names must be separated by spaces.
source_or_object_files
Optional C files (.c), object files (.o), or archived libraries (.a).
These are DirectC or PLI applications that you want VCS to link
into the binary executable file along with the object files from your
Verilog source files.
options
Compile-time options that control how VCS compiles your Verilog
source files. For details, see “Basic Compile-Time Options” on
page 1-14.
The following is an example command line used at compile-time:
vcs top.v toil.v -RI +v2k
By default, VCS names the executable binary file simv. You can
specify a different name with the -o compile-time option.