User guide

19-13
Using the VCS / SystemC Cosimulation Interface
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end module
Controlling Time Scale and Resolution in a SystemC
Module Contained in a Verilog Design
To control the time resolution of your SystemC module, create a static
global object that initializes the timing requirements for the module.
This can be a separate file that is included as one of the .cpp files for
the design.
Sample contents for this file are:
include <systemc.h>
class set_time_resolution {
public:
set_time_resolution()
{
try {
sc_set_time_resolution(10, SC_PS);
sc_set_default_time_unit(100, SC_PS);
}
catch( const sc_exception& x ) {
cerr << "setting time resolution/default time unit
failed: " <<
x.what() << endl;
}
}
};
static int SetTimeResolution()
{
new set_time_resolution();
return 42;
}
static int time_resolution_is_set = SetTimeResolution();