User guide

19-12
Using the VCS / SystemC Cosimulation Interface
initial
begin
counter = 0;
end
always @(output_data_ready)
begin
counter = counter + 1;
$display("Display : %d", result);
if (counter >= 24)
begin
$finish;
end
end
endmodule
You instantiate the SystemC model as follows in the Verilog part of
the design:
File: tb.v
module testbench ();
reg clock;
wire reset;
wire input_valid;
wire [31:0] sample;
wire output_data_ready;
wire [31:0] result;
// Stimulus is the SystemC model.
stimulus stimulus1(.sample(sample),
.input_valid(input_valid),
.reset(reset),
.clk(clock));
// Display is the Verilog model.
display display1(.output_data_ready(output_data_ready),
.result(result));