User guide

19-11
Using the VCS / SystemC Cosimulation Interface
Instantiating the Wrapper and Coding Style
You instantiate the SystemC wrapper just like a Verilog module. For
example, consider the following SystemC module in a file named
stimulus.h:
SC_MODULE(stimulus) {
sc_out<sc_logic> reset;
sc_out<sc_logic> input_valid;
sc_out<sc_lv<32> > sample;
sc_in_clk clk;
sc_int<8> send_value1;
unsigned cycle;
SC_CTOR(stimulus)
: reset("reset")
, input_valid("input_valid")
, sample("sample")
, clk("clk")
{
SC_METHOD(entry);
sensitive_pos(clk);
send_value1 = 0;
cycle = 0;
}
void entry();
};
The Verilog model is display:
File: display.v
module display (output_data_ready, result);
input output_data_ready;
input [31:0] result;
integer counter;