User guide

19-7
Using the VCS / SystemC Cosimulation Interface
Input Files Required
To run a cosimulation with a Verilog design containing SystemC
instances, you need to provide the following files:
• SystemC source code
- You can directly write the entity-under-test source code or
generate it with other tools.
- Any other C or C++ code for the design
• Verilog source code (.v extensions) including:
- A Verilog top-level simulation that instantiates the interface
wrapper and other Verilog modules. These wrapper files are
generated by a utility and you don’t need to do anything to these
files (see “Generating the Wrapper for SystemC Modules” on
page 19-8 and “Instantiating the Wrapper and Coding Style” on
page 19-11).
- Any other Verilog source files for the design
• An optional port mapping file. If you do not provide this file, the
interface uses the default port mapping definition. For details of
the port mapping file, see “Using a Port Mapping File” on page
19-26.
• An optional data type mapping file. If you don’t write a data type
mapping file, the interface uses the default one in the VCS
installation. For details of the data type mapping files, see “Using
a Data Type Mapping File” on page 19-27.