User guide

19-6
Using the VCS / SystemC Cosimulation Interface
Verilog Design Containing SystemC Leaf Modules
To cosimulate a Verilog design that contains SystemC and Verilog
modules, you need to import one or more SystemC instances into
the Verilog design. Using the VCS / SystemC Cosimulation Interface,
you generate a wrapper and include it in the Verilog design for each
SystemC instance. The ports of the created Verilog wrapper are
connected to signals that are attached to the ports of the
corresponding SystemC modules.
Figure 19-1 illustrates VCS DKI communication.
Figure 19-1 VCS DKI Communication of an Verilog Design Containing
SystemC Modules
DKI
clk
reset
in
out
rdy_read
SystemC simulator
HDL environment
clk
reset
in
out
rdy_read
HDL interface to the
SystemC simulator
SystemC interface to the HDL environment
Automatically generated by the tool
Managed by the tool
Block 2
Block 1
Block 2
Block 3
Block 1
SystemC source code
entity-under-test
HDL source code