User guide

19-5
Using the VCS / SystemC Cosimulation Interface
Note:
There are examples of Verilog instantiated in SystemC, and
SystemC instantiated in Verilog, in the $VCS_HOME/doc/
examples/osci_dki directory.
Supported Port Data Types
SystemC types are restricted to the sc_clock, sc_bit, sc_bv, sc_logic,
sc_lv, sc_int, sc_uint, sc_bigint, and sc_biguint data types. Native C/
C++ types are restricted to the uint, uchar, ushort, int, bool, short,
char, long and ulong types.
Verilog ports are restricted to bit, bit vector and signed bit vector types.
Inout ports that cross the cosimulation boundary between SystemC
and Verilog must observe the following restrictions:
• SystemC port types must be sc_inout_rv<> or sc_inout_resolved
and must be connected to signals of type sc_signal_rv<> or
sc_signal_resolved.
• Verilog port types must be bit_vector or bit.
• You need to create a port mapping file, as described in “Using a
Port Mapping File” on page 19-26, to specify the SystemC port
data types as sc_lv (for a vector port) or sc_logic (for a scalar port).