User guide

19-4
Using the VCS / SystemC Cosimulation Interface
• Using a Customized SystemC Installation
Usage Scenario Overview
The usage models for the VCS /SystemC Cosimulation Interface are:
• Verilog designs containing SystemC modules
• SystemC designs containing Verilog modules
The major steps involved to create a simulation for each of these
design scenarios are:
1. Analyze the SystemC and Verilog modules from the bottom of the
design to the top.
2. For Verilog designs containing SystemC modules:
- Use the syscan file.cpp:model command to analyze
SystemC modules used in the Verilog domain.
- Use the syscan f.cpp... command to compile other
SystemC modules in the design.
- Use the vlogan command to analyze Verilog files.
- Use the vcs -sysc command to build the simulation.
3. For SystemC designs containing Verilog modules:
-Use the vlogan -sc_model command to analyze Verilog files
containing modules used in the SystemC domain.
- Use the syscan f.cpp... command to compile SystemC
files.
- Use the syscsim command to build the simulation.