User guide

1-12
Getting Started
Figure 1-1 Basic VCS Compilation and Simulation Flow
Simulation
simv
Debug
VCS
Simulate
Step1: Compilation
% vcs mem.v cpu.v
Verilog
Code
(mem.v, cpu.v)
Executable
VPD
Files
Step 2: Simulation
% simv
DVE
Command Line
Interface
Interactive Debugging