User guide

19-3
Using the VCS / SystemC Cosimulation Interface
Notes:
• There are examples of Verilog instantiated in SystemC and
SystemC instantiated in Verilog in the
$VCS_HOME/doc/ examples/osci_dki directory.
• The interface supports the following compilers:
- Linux: gnu 3.3.6 compiler
- Solaris: SC 8.0, and gcc 3.3.6 (default) and 3.4.6
• The VCS / SystemC Cosimulation Interface supports 32-bit
simulation 32-bit as well as 64-bit (VCs flag -full64)
simulation. Do not use the -comp64 compile-time options with
the interface.
• The gcc compilers, along with a matching set of GNU tools, are
available on the Synopsys FTP server for download. For more
information e-mail [e-mail].
The usage models for the VCS / SystemC Cosimulation Interface,
depending on the type of cosimulation you want to perform. This
chapter describes these models in the following sections:
• Usage Scenario Overview
• Verilog Design Containing SystemC Leaf Modules
• SystemC Designs Containing Verilog Modules
• Using a Port Mapping File
• Using a Data Type Mapping File
• Debugging the SystemC Portion of a Design
• Transaction Level Interface