User guide

19-2
Using the VCS / SystemC Cosimulation Interface
With the interface you can use the most appropriate modeling
language for each part of the system, and verify the correctness of
the design. For example, the VCS / SystemC Cosimulation Interface
allows you to:
• Use a SystemC module as a reference model for the Verilog RTL
design under test in your testbench.
• Verify a Verilog netlist after synthesis with the original SystemC
testbench
• Write testbenches in SystemC to check the correctness of Verilog
designs
• Import legacy Verilog IP into a SystemC description
• Import third-party Verilog IP into a SystemC description
• Export SystemC IP into a Verilog environment when only a few
of the design blocks are implemented in SystemC
• Use SystemC to provide stimulus to your design.
The VCS / SystemC Cosimulation Interface creates the necessary
infrastructure to cosimulate SystemC models with Verilog models.
The infrastructure consists of the required build files and any
generated wrapper or stimulus code. VCS writes these files in
subdirectories in the ./csrc directory. To use the interface, you don’t
need to do anything to these files.
During cosimulation, the VCS / SystemC Cosimulation Interface is
responsible for:
• Synchronizing the SystemC kernel and VCS
• Exchanging data between the two environments