User guide

18-55
DirectC Interface
}
This function declares a vec32 array of three elements named
holder. It uses three elements because its parameters are 68-bit
regs so we need an element for every 32 bits and one more for the
remaining four bits.
The Verilog code displays the following:
r1=111zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz000000000000000000000000000000000
r2=111zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz000000000000000000000000000000000
void vc_get2stVector(vc_handle, U *)
void vc_put2stVector(vc_handle, U *)
Passes a two state vector by reference to a vc_handle to and from
an array in C/C++ function. vc_get2stVector receives the vector
from Verilog and passes it to the array and vc_put4stVector
passes the array to Verilog.
There routines, just like the vc_get4stVector and
vc_put4stVector routines, work only if there are enough elements
in the array for all the bits in the vector. The array must have an
element for every 32 bit in the vector plus an additional element for
any remaining bits.
The only differences between these routines and the
vc_get4stVector and vc_put4stVector routines are the type
of data they pass, two or four state simulation values, and the type
you declare for the array in the C/C++ function.