User guide

18-32
DirectC Interface
The access routines were named to help you to remember their
function. Routine names beginning with vc_get are for retrieving
data from the descriptor for the Verilog parameter. Routine names
beginning with vc_put are for passing new values to these
descriptors.
These routines can convert Verilog representation of simulation
values and strings to string representation in C/C++. Strings can also
be created in a C/C++ function and passed to Verilog but you should
bear in mind that they can be overwritten in Verilog. So you should
copy them to local buffers if you want them to persist.
The following are the access routines, their parameters, and return
values, and examples of how they are used. There is a summary of
the access routines at the end of this chapter; see "Summary of
Access Routines" on page 18-77.
int vc_isScalar(vc_handle)
Returns a 1 value if the vc_handle is for a one-bit reg or bit; returns
a 0 value for a vector reg or bit or any memory including memories
with scalar elements. For example:
extern "A" void scalarfinder(input reg r1,
input reg [1:0] r2,
input reg [1:0] array [1:0] r3,
input reg array [1:0] r4);
module top;
reg r1;
reg [1:0] r2;
reg [1:0] r3 [1:0];
reg r4 [1:0];
initial
scalarfinder(r1,r2,r3,r4);
endmodule