User guide

18-30
DirectC Interface
Using vc_handle
In the function header, the vc_handle for a Verilog reg, bit, or memory
is based on the order that you declare the vc_handle and the order
that you entered its corresponding reg, bit, or memory in the function
call in your Verilog code. For example, you could have declared the
function and called it in your Verilog code as follows:
This is using abstract access so VCS created descriptors for bit1 and
bit2. These descriptors contain information about their value, but also
other information such as whether they are scalar or vector, and
whether they are simulating in two or four-state simulation.
extern "A" void my_function( input bit [31:0] r1,
input bit [32:0] r2);
module dev1;
reg [31:0] bit1;
reg [32:0] bit2;
initial
begin
.
.
.
my_function(bit1,bit2);
.
.
.
end
endmodule
Declare the function
Enter first bit1 then bit2 as arguments
in the function call