User guide

18-15
DirectC Interface
For a four-state vector (denoted by the keyword reg) the Verilog data
is stored in type vec32, which for abstract access is defined as follows:
typedef unsigned int U;
typedef struct { U c; U d;} vec32;
So type vec32* has two members of type U; member c is for control
bits and member d is for data bits.
For a two state vector bit the Verilog data is stored in type U*.
Vector values are stored in arrays of chunks of 32 bits. For four-state
vectors there are chunks of 32 bits for data values and 32 bits for
control values. For two-state vectors there are chunks of 32 bits for
data values.
Figure 18-4 Storing Vector Values
Long vectors, more than 32 bits, have their value stored in more than
one group of 32 bits and can accessed by chunk. Short vectors, 32
bits or less, are stored in a single chunk.
control
data
data
four state
two state