User guide

1-4
Getting Started
• OpenVera Assertions (OVA) — provides an easy and concise
way to describe sequences of events, and facilities to test for their
occurrence. VCS natively compiles OVA. For details on OVA, see
Chapter 20, "Using OpenVera Assertions" and the OpenVera
Language Reference Manual: Assertions volume. Many of the
implemented SystemVerilog assertions constructs are
functionally comparable to OpenVera assertion constructs.
• OpenVera Native Testbench — a testbench language that is a
subset of the OpenVera testbench language. VCS can natively
compile testbench files written in OpenVera testbench constructs
into the simv executable file, along with Verilog source files and
OpenVera Assertions (OVA) files. For details on OpenVera Native
Testbench, see Chapter 21, "OpenVera Native Testbench".
• Discovery Visualization Environment (DVE) — the new graphical
debugging environment. You can use DVE to trace signals of
interest while viewing annotated values in the source code or
schematic diagrams. You can also compare waveforms, extract
specific signal information, and generate testbenches based on
waveform outputs. For details, see Chapter 5, "Using the
Discovery Visual Environment" and the Discovery Visual
Environment User Guide. DVE is in the process of replacing
VirSim.
• Built-In Coverage Metrics — a comprehensive built-in coverage
analysis functionality that includes condition, toggle, line,
finite-state-machine (FSM), path, and branch coverage. You can
use coverage metrics to determine the quality of coverage of your
verification test and focus on creating additional test cases. You
only need to compile once to run both simulation and coverage
analysis. For details, see the VCS Coverage Metrics User Guide.