User guide

18-5
DirectC Interface
Using abstract access is “safer” because the library of accessory
functions for abstract access has error messages to help you to debug
the interface between the C/C++ and Verilog. With direct access,
errors simply result in segmentation faults, memory corruption, etc.
Abstract access can be generalized more easily for your C/C++
function. For example, with open arrays you can call the function with
8-bit arguments at one point in your Verilog design and call it again
some place else with 32-bit arguments. The accessory functions can
manage the differences in size. With abstract access you can have
the size of a parameter returned to you. With direct access you must
know the size.
How C/C++ Functions Work in a Verilog Environment
Like Verilog functions, and unlike Verilog tasks, no simulation time
elapses during the execution of a C/C++ function.
C/C++ functions work in two-state and four-state simulation and in
some cases work better in two-state simulation. Short vector values,
32-bits or less, are passed by value instead of by reference. Using
two-state simulation makes a difference in how you declare a C/C++
function in your Verilog code.
The parameters of C/C++ functions, are analogous to the arguments
of Verilog tasks. They can be input, output, or inout just like the
arguments of Verilog tasks. You don’t specify them as such in your
C code, but you do when you declare them in your Verilog code.
Accordingly your Verilog code can pass values to parameters
declared to be input or inout, but not output, in the function declaration
in your Verilog code, and your C function can only pass values from
parameters declared to be inout or output, but not input, in the function
declaration in your Verilog code.