User guide

1-3
Getting Started
What VCS Supports
VCS provides fully featured implementations of the following:
• The Verilog language as defined in the IEEE Standard Hardware
Description Language Based on the Verilog Hardware
Description Language (IEEE Std 1364-1995) and the Standard
Verilog Hardware Description Language (IEEE Std 1364-2001).
• The SystemVerilog 3.1a language (with some exceptions) as
defined in SystemVerilog 3.1a Accellera’s Extensions to Verilog.
In addition, VCS supports interfaces to a variety of other simulators
and models, including (but not limited to) user PLI applications
conforming to IEEE Std 1363-1995, delay calculators, SDF delay
annotation, and Synopsys Logic Modeling SmartModels
®
.
Main Components of VCS
In addition to its standard Verilog compilation and simulation capabilities,
VCS includes the following integrated set of features and tools:
• SystemVerilog — an extension of the Verilog language that adds
new design, testbench, and assertion constructs. For details on
SVA, see Chapter 23, "SystemVerilog Assertion Constructs",
Chapter 22, "SystemVerilog Design Constructs", and Chapter 24,
"SystemVerilog Testbench Constructs".