User guide

17-20
Using the PLI
Example 2
The following specifications enable most interactive commands for
most of the modules in a design. They then change the ACC
capabilities preventing breakpoint and force commands in instances
of modules in Verilog libraries and modules designated as cells with
the ‘celldefine compiler directive.
acc+=rw,cbk,frc:top+ acc:=rw:%CELL
Here the first specification enables the interactive commands that are
enabled by the rw, cbk, and frc capabilities for module top, which
in this example is the top-level module of the design, and all module
instances under it. The second specification limits the interactive
commands for the specified modules to only those enabled by the rw
(same as r) capability.
Using the PLI Table File
You specify the PLI table file with the -P compile-time option, followed
by the name of the PLI table file (by convention, the PLI table file has
a .tab extension). For example:
-P pli.tab
When you enter this option on the vcs command line, you can also
enter C source files, or compiled .o object files or .a libraries on the
vcs command line, to specify the PLI application that you want to link
with VCS. For example:
vcs -P pli.tab pli.c my_design.v