User guide

1-1

Getting Started

Getting Started 1

VCS

is a high-performance, high-capacity Verilog

simulator that

incorporates advanced, high-level abstraction verification

technologies into a single open native platform.

VCS enables you to analyze, compile, and simulate Verilog design

descriptions. It also provides you with a set of simulation and

debugging features to validate your design. These features provide

capabilities for source-level debugging and simulation result viewing.

VCS supports all levels of design descriptions, but is optimized for

the behavioral and register transfer levels.

VCS accelerates complete system verification by delivering the

fastest and highest capacity Verilog simulation for RTL functional

verification.

In addition, VCS supports Synopsys DesignWare IP, the VCS

Verification Library, VMC models, and the Vera testbench tool.