User guide

17-17
Using the PLI
Specifying ACC Capabilities for VCS Debugging
Features
The format for specifying ACC capabilities for VCS debugging
features is as follows:
acc=|+=|-=|:=capabilities:module_names[+]|%CELL|*
Here:
acc
Keyword that begins a line for specifying ACC capabilities.
=|+=|-=|:=
Operators for adding, removing, or changing ACC capabilities.
capabilities
Comma separated list of ACC capabilities.
module_names
Comma-separated list of module identifiers. The specified ACC
capabilities will be added, removed, or changed for all instances
of these modules.
+
Specifies adding, removing, or changing the ACC capabilities for
not only the instances of the specified modules but also the
instances hierarchically under the instances of the specified
modules.
%CELL
Specifies all modules compiled under the
‘celldefine compiler
directive and all modules in Verilog library directories and library
files (as specified with the
-y and -v compile-time options.)
*
Specifies all modules in the design. Using a wildcard character is
no more efficient than using the
+cli compile-time option.