User guide

17-16
Using the PLI
acc+= rw,tchk:top,bot acc-=tchk:top
This example adds the ACC capabilities for reading and writing to
nets and registers, and for backannotating timing check delays, to
these PLI functions, and enables them to do these things in all
instances of modules top and bot. It then removes the ACC
capability for backannotating timing check delay values from these
PLI functions in all instances of module top.
Example 2
$value_passer size=0 args=2 call=value_passer persistent
acc+=rw:%TASK acc-=rw:%CELL
This example adds the ACC capability to read from and write to the
values of nets and registers to these PLI functions. It enables them
to do these things in all instances of modules declared in module
definitions that contain the $value_passer user-defined system task.
The example then removes the ACC capability to read from and write
to the values of nets and registers, from these PLI functions, in module
definitions compiled under the
‘celldefine compiler directive and
all module definitions in Verilog library directories and library files.
Example 3
$set_true size=16 call=set_true acc+=rw:*
This example adds the ACC capability to read from and write to the
values of nets and registers to the PLI functions. It enables them to
do this throughout the entire design.