User guide

17-15
Using the PLI
+
Specifies adding, removing, or changing the ACC capabilities for
not only the instances of the specified modules but also the
instances hierarchically under the instances of the specified
modules.
%CELL
Enables, disables, or changes (depending on the operator) the
ability of the PLI function to use the ACC capability in all instances
of module definitions compiled under the
‘celldefine compiler
directive and all module definitions in Verilog library directories
and library files (as specified with the
-y and -v compile-time
options).
%TASK
Enables, disables, or changes (depending on the operator) the
ability of the PLI function to use the ACC capability in all instances
of module definitions that contain the user-defined system task or
system function associated with the PLI function.
*
Enables, disables, or changes (depending on the operator) the
ability of the PLI function to use the ACC capability throughout the
entire design. Using wildcard characters could seriously impede
the performance of VCS.
Note:
There are no blank spaces when specifying ACC capabilities.
The following examples are the PLI specification examples from the
previous section with ACC capabilities added to them. The examples
wrap to more than one line, but when you edit your PLI table file, be
sure there are no line breaks in these lines.
Example 1
$val_proc call=val_proc check=check_proc misc=misc_proc